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fujitsu semiconductor data sheet copyright?2011 fujitsu semiconductor limited all rights reserved 2011.6 memory fram 128k (16 k 8) bit spi MB85RS128A description MB85RS128A is a fram (ferroelectric random acce ss memory) chip in a configuration of 16,384 words 8 bits, using the ferroelectric process and silic on gate cmos process technologies for forming the nonvolatile memory cells. MB85RS128A adopts the serial peripheral interface (spi). the MB85RS128A is able to retain data without using a back-up ba ttery, as is needed for sram. the memory cells used in the MB85RS128A can be used for 10 10 read/write operations, which is a significant improvement over the number of read and writ e operations supported by flash memory and e 2 prom. MB85RS128A does not take long time to write data unlike flash memories nor e 2 prom, and MB85RS128A takes no wait time. features ? bit configuration : 16,384 words 8 bits ? operating power supply voltage : 3.0 v to 3.6 v ? operating frequency : 25 mhz (max) ? serial peripheral interface : spi (serial peripheral interface) correspondent to spi mode 0 (0, 0) and mode 3 (1, 1) ? operating temperature range : ?40 c to +85 c ? data retention : 10 years ( + 55 c) ? high endurance : 10 billion read/writes ? package : 8-pin plastic sop (fpt-8p-m02) ds501-00008-0v01-e
MB85RS128A 2 ds501-00008-0v01-e pin assignment pin functional descriptions pin no. pin name functional description 1cs chip select this is an input pin to make chips select. when cs is ?h?, device is in deselect (standby) status as long as device is not write status internally, and so becomes high-z. other in- puts from pins are ignored for this time. when cs is ?l?, device is in select (active) status. cs has to be ?l? before inputting op-code. 3wp write protect this is a pin to control writi ng to a status register. when wp is ?l?, writing to a status register is not operated. 7hold hold this pin is used to interrupt serial input /output without making chips deselect. when hold is ?l?, hold operation is activated, so becomes high-z, sck and si become don?t care. while the hold operation, cs has to be retained ?l?. 6sck serial clock this is a clock input pin to input/output seri al data. si is loaded synchronously to a rising edge, so is output synchronously to a falling edge. 5si serial data input this is an input pin of serial data. this inputs op-code, address, and writing data. 2so serial data output this is an output pin of serial data. readi ng data of fram memory cell array and status register data are output. this is high-z during standby. 8v cc supply voltage 4 gnd ground gnd si so v cc sck wp cs hold 8 7 6 5 4 3 2 1 (top view) (fpt-8p-m02)
MB85RS128A ds501-00008-0v01-e 3 block diagram sck so si serial-parallel con v erter fram cell array 16,3 8 4 8 col u mn decoder/sense amp/ w rite amp fram stat u s register data register parallel-serial con v erter control circ u it address co u nter ro w -decoder cs w p hold
MB85RS128A 4 ds501-00008-0v01-e spi mode MB85RS128A corresponds to the spi mode 0 (cpol = 0, cpha = 0) , and spi mode 3 (cpol = 1, cpha = 1) . sck si cs sck si cs 76543210 76543210 msb lsb msb lsb spi mode 0 spi mode 3
MB85RS128A ds501-00008-0v01-e 5 serial peripheral interface (spi) MB85RS128A works as a slave of spi. more than 2 devices can be connected by using microcontroller equipped with spi port. by using a microcontroller not equipped with spi port, si and so can be bus connected to use. sck ss1 hold1 mosi miso ss2 hold2 sck cs hold si so sck cs hold si so mb 8 5rs12 8 amb 8 5rs12 8 a sck cs hold si so mb 8 5rs12 8 a spi microcontroller mosi : master out slave in miso : master in slave out ss : slave select system configuration with spi port system configuration without spi port microcontroller
MB85RS128A 6 ds501-00008-0v01-e status register op-code MB85RS128A accepts 6 kinds of command specified in op-code. op-code is a code composed of 8 bits shown in the table below. do not input invalid codes other than those codes. if cs is risen while inputting op-code, the command are not performed. bit no. bit name function 7wpen status register write protect this is a bit composed of nonvolatile memories (fram). wpen is related to wp input to protect writing to a status register (refer to ? writing protect?). writing with the wrsr command and reading with the rdsr command are possible. 6 to 4 not used bits these are bits composed of nonvolatile memories, writing with the wrsr command is possible, and ?000? is written before shipment. these bits are not used but they are re ad with the rdsr command. 3 bp1 block protect this is a bit composed of nonvolatile memory (fram). this defines block size for writing protect with the write command (refer to ? block protect?). writing with the wr sr command and reading with the rdsr command are possible. 2 bp0 1wel write enable latch this indicates fram memory and status register are writable. the wren command is for setting, and the wrdi command is for resetting. with the rdsr command, reading is possible but writing is not possible with the wrsr command. wel is reset after the following operations. the time when power is up. the time when the wrdi command is input. the time when the wrsr command is input. the time when the wr ite command is input. 0 0 this is a bit fixed to ?0?. name description op-code wren set write enable latch 0000 0110 b wrdi reset write enable latch 0000 0100 b rdsr read status register 0000 0101 b wrsr write status register 0000 0001 b read read memory code 0000 0011 b write write memory code 0000 0010 b
MB85RS128A ds501-00008-0v01-e 7 command ? wren the wren command sets wel (write enable latch) . wel has to be set with the wren command before writing operation (wrsr co mmand and write command) . ? wrdi the wrdi command resets wel (write enable la tch) . writing operation (write command and wrsr command) are not performed when wel is reset. s o s ck s i c s 00000110 high-z 7 6 5 4 3 2 1 0 invalid invalid s o s ck s i c s 00000100 high-z 7 6 5 4 3 2 1 0 invalid invalid
MB85RS128A 8 ds501-00008-0v01-e ? rdsr the rdsr command reads status regist er data. after op-code of rdsr is input to si, 8-cycle clock is input to sck. the si value is invalid for this time. so is output synchronously to a falli ng edge of sck. continuously reading status register is enabled by keep on sending sck before rising cs with the rdsr command. ? wrsr the wrsr command writes data to the nonvolatile memo ry bit of status register. after performing wrsr op-code to a si pin, 8 bits writing da ta is input. wel (write enable latch) is not able to be written with wrsr command. a si value correspondent to bit 1 is ignored. bit 0 of the status register is fixed to ?0? and cannot be written. the si value corresponding to bit 0 is ignored. s o s ck s i c s 00000101 high-z 7 6 5 4 3 2 1 0 invalid m s b 7 6 5 4 3 2 1 0 data out l s b invalid s o s ck s i c s 00000001 7 6 5 4 3 2 1 0 data in m s b 7 6 5 4 3 2 1 0 high-z l s b 7654 3 210 instruction
MB85RS128A ds501-00008-0v01-e 9 ? read the read command reads fram memory cell array dat a. arbitrary 16 bits address and op-code of read are input to si. the most significant address bit is inva lid. then, 8-cycle clock is input to sck. so is output synchronously to the falling edge of sck. while reading, the si value is invalid. when cs is risen, the read command is completed, but keep on r eading address with automatic incr ement is enabled by continuously sending clock for 8 cycles each to sck before cs is risen. when it reaches t he most significant address, it rolls over to come back to the starting addr ess, and reading cycle keeps on infinitely. ? write the write command writes data to fr am memory cell array. write op-code, arbitrary 16 bits of address and 8 bits of writing data are input to si. the most si gnificant address bit is inva lid. when 8 bits of writing data is input, data is written to fram memory cell array. risen cs will terminate the write command, but if you continue sending the writin g data for 8 bits each before cs is risen, it is possible to continue writing with automatic address increment. when it reaches t he most significant address, it rolls over, comes back to the starting address, and writing cycle can be continued infinitely. so sck si cs 00 0 0x 11210 msb 7 6 5 4 3 2 1 0 data o u t msb high-z lsb 420 1 in v alid 13 12 11 10 9 8 25 24 23 22 21 20 19 1 8 31 30 29 2 8 27 26 op-code 00 1 11 13 x3 5 16- b it address in v alid lsb 20 1 3 64 5 7 so sck si cs 00 0 0x 11210 msb 7 6 5 4 3 2 1 0 data in msb high-z lsb 420 1 13 12 11 10 9 8 25 24 23 22 21 20 19 1 8 31 30 29 2 8 27 26 op-code 00 0 11 13 x3 5 16- b it address lsb 20 1 3 64 5 7
MB85RS128A 10 ds501-00008-0v01-e block protect writing protect block is configured by the write co mmand with bp1, bp0 value of the status register. writing protect writing operation of the write co mmand and the wrsr command are protected with the value of wel, wpen, wp as shown in the table. hold operation hold status is retained without aborting a command if hold is ?l? while cs is ?l?. the timing for starting and ending hold status depends on th e sck to be ?h? or ?l? when a hold pin input is transited as shown in the diagram below. arbitrary command operation is interrupted in hold status, sck and si inputs become don?t care. and, so becomes high-z while reading command (rdsr, read) . if cs is risen with hold status, a command is aborted and device is reset. bp1 bp0 protected block 00none 0 1 3000 h to 3fff h (upper 1/4) 1 0 2000 h to 3fff h (upper 1/2) 1 1 0000 h to 3fff h (all) wel wpen wp protected blocks unprotected blocks status register 0 x x protected protected protected 1 0 x protected unprotected unprotected 1 1 0 protected unprotected protected 1 1 1 protected unprotected unprotected s ck c s hold condition hold hold condition
MB85RS128A ds501-00008-0v01-e 11 absolute maximum ratings *:these parameters are based on the condition that v ss is 0 v. warning: semiconductor devices can be permanently dama ged by application of stress (voltage, current, temperature, etc.) in excess of absolute ma ximum ratings. do not exceed these ratings. recommended operating conditions *:these parameters are based on the condition that v ss is 0 v. warning: the recommended operating co nditions are required in order to ensure the normal operation of the semiconductor device. all of the device's el ectrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affe ct reliability and could result in device failure. no warranty is made with respect to uses, operat ing conditions, or combinations not represented on the data sheet. users considering application out side the listed conditions are advised to contact their representatives beforehand. parameter symbol rating unit min max power supply voltage* v cc ? 0.5 + 4.0 v input voltage* v in ? 0.5 v cc + 0.5 v output voltage* v out ? 0.5 v cc + 0.5 v operating temperature t a ? 40 + 85 c storage temperature tstg ? 40 + 125 c parameter symbol value unit min typ max power supply voltage* v cc 3.0 3.3 3.6 v input high voltage* v ih v cc 0.8 v cc + 0.5 v input low voltage* v il ? 0.5 + 0.6 v operating temperature t a ? 40 + 85 c
MB85RS128A 12 ds501-00008-0v01-e electrical characteristics 1. dc characteristics (within recommended operating conditions) parameter symbol condition value unit min typ max input leakage current i li v in = 0 v to v cc 10 a output leakage current i lo v out = 0 v to v cc 10 a operating power supply current i cc sck = 25 mhz 510ma standby current i sb all inputs v ss or sck = si = cs = v cc 350 a output high voltage v oh i oh = ? 2 ma v cc 0.8 v output low voltage v ol i ol = 2 ma 0.4 v
MB85RS128A ds501-00008-0v01-e 13 2. ac characteristics (within recommended operating conditions) ac test condition power supply voltage : 3.0 v to 3.6 v operation temperature : ? 40 c to + 85 c input voltage magnitude : 0.3 v to 2.7 v input rising time : 5 ns input falling time : 5 ns input judge level : v cc /2 output judge level : v cc /2 parameter symbol value unit min max sck clock frequency f ck 025mhz clock high time t ch 20 ns clock low time t cl 20 ns chip select set up time t csu 10 ns chip select hold time t csh 10 ns output disable time t od 20 ns output data valid time t odv 18 ns output hold time t oh 0 ns deselect time t d 60 ns data in rise time t r 50 ns data fall time t f 50 ns data set up time t su 5 ns data hold time t h 5 ns hold set up time t hs 10 ns hold hold time t hh 10 ns hold output floating time t hz 20 ns hold output active time t lz 20 ns
MB85RS128A 14 ds501-00008-0v01-e ac load equivalent circuit 3. pin capacitance parameter symbol value unit min max output capacitance c o 10 pf input capacitance c i 10 pf 3 0 pf output 3 . 3 v 1.2 k 0.95 k
MB85RS128A ds501-00008-0v01-e 15 timing diagram ? serial data timing ? hold timing sck cs v a lid in si so high-z : don't c a re t csu t ch t cl t su t h t odv t oh t od t csh t d high-z s ck c s s o t h s t h s t hh t hh t hh t hh t hz t lz t hz t lz t h s t h s hold high-z high-z
MB85RS128A 16 ds501-00008-0v01-e power on/off sequence notes on use after the ir reflow completed, it is not guaranteed to save the data written prior to the ir reflow. parameter symbol value unit min max cs level hold time at power off tpd 200 ns cs level hold time at power on tpu 85 ns power supply rising time tr 0.05 200 ms gnd cs >v cc 0.8* tpd tp u tr v il (m a x) 1.0 v v ih (min) 3.0 v v cc cs : don't c a re cs >v cc 0.8* cs cs gnd v il (m a x) 1.0 v v ih (min) 3.0 v v cc * : cs (max) < v cc + 0.5 v note : ? because turning the power-on from an intermediat e level may cause malfunctions, when the power is turned on, v cc is required to be started from 0 v. ? if the device does not operate with in the specified conditions of read cycle, write cycle, power on/ off sequence, memory data can not be guaranteed.
MB85RS128A ds501-00008-0v01-e 17 ordering information note : please confirm the ordering info rmation with the sales representatives. part number package remarks tbd 8-pin plastic sop (fpt-8p-m02) tbd 8-pin plastic sop (fpt-8p-m02) embossed carrier tape
MB85RS128A 18 ds501-00008-0v01-e package dimension please check the latest package dimension at the following url. http://edevice.fujitsu.com/package/en-search/ 8-pin pl as tic sop le a d pitch 1.27 mm p a ck a ge width p a ck a ge length 3.9 mm 5.05 mm le a d s h a pe g u llwing se a ling method pl as tic mold mo u nting height 1.75 mm max weight 0.06 g 8-pin pl as tic sop (fpt-8p-m02) (fpt-8p-m02) c 2002-2010 fujitsu semiconductor limited f08004s-c-4-9 1.27(.050) 3.900.30 6.000.40 .199 ?.008 +.010 ?0.20 +0.25 5.05 0.13(.005) m (.154.012) (.236.016) 0.10(.004) 14 5 8 0.440.08 (.017.003) ?0.07 +0.03 0.22 .009 +.001 ?.003 45 0.40(.016) "a" 0~8 0.25(.010) (mo u nting height) det a il s of "a" p a rt 1.550.20 (.061.008) 0.500.20 (.020.008) 0.600.15 (.024.006) 0.150.10 (.006.004) (st a nd off) 0.10(.004) * 1 * 2 dimen s ion s in mm (inche s ). note: the v a l u e s in p a renthe s e s a re reference v a l u e s . note 1) * 1 : the s e dimen s ion s incl u de re s in protr us ion. note 2) * 2 : the s e dimen s ion s do not incl u de re s in protr us ion. note 3) pin s width a nd pin s thickne ss incl u de pl a ting thickne ss . note 4) pin s width do not incl u de tie b a r c u tting rem a inder.
MB85RS128A ds501-00008-0v01-e 19 memo
MB85RS128A fujitsu semiconductor limited nomura fudosan shin-yokohama bldg . 10-23, shin-yokohama 2-chome, kohoku-ku yokohama kanagawa 222-0033, japan tel: +81-45-415-5858 http://jp.fujitsu.com/fsl/en/ for further information please contact: north and south america fujitsu semiconductor america, inc. 1250 e. arques avenue, m/s 333 sunnyvale, ca 94085-5401, u.s.a. tel: +1-408-737-5600 fax: +1-408-737-5999 http://us.fujitsu.com/micro/ europe fujitsu semiconductor europe gmbh pittlerstrasse 47, 63225 langen, germany tel: +49-6103-690-0 fax: +49-6103-690-122 http://emea.fujitsu.com/semiconductor/ korea fujitsu semiconductor korea ltd. 902 kosmo tower building, 1002 daechi-dong, gangnam-gu, seoul 135-280, republic of korea tel: +82-2-3484-7100 fax: +82-2-3484-7111 http://kr.fujitsu.com/fsk/ asia pacific fujitsu semiconductor asia pte. ltd. 151 lorong chuan, #05-08 new tech park 556741 singapore tel : +65-6281-0770 fax : +65-6281-0220 http://sg.fujitsu.com/semiconductor/ fujitsu semiconductor shanghai co., ltd. rm. 3102, bund center, no.222 yan an road (e), shanghai 200002, china tel : +86-21-6146-3688 fax : +86-21-6335-1605 http://cn.fujitsu.com/fss/ fujitsu semiconductor pacific asia ltd. 10/f., world commerce centre, 11 canton road, tsimshatsui, kowloon, hong kong tel : +852-2377-0226 fax : +852-2376-3269 http://cn.fujitsu.com/fsp/ specifications are subject to change without notice. for further information please contact each office. all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with sales representatives before ordering. the information, such as descriptions of function and applicatio n circuit examples, in this docum ent are presented solely for t he purpose of reference to show examples of operations and uses of fujitsu semiconductor device; fujitsu semiconductor does not warrant proper operation of the device with respect to use based on such informa tion. when you develop equipment incorporat ing the device based on such information, you must assume any re sponsibility arising out of such use of the information. fujitsu semiconductor assumes no liability for any damages whatsoever arising out of the use of the information. any information in this document, including descriptions of function and schematic di agrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent ri ght or copyright, or any other right of fujitsu semiconductor or any third party or does fujitsu semiconductor warrant non-infringement of any third-part y's intellectual property right or other ri ght by using such information. fujitsu semiconductor assumes no liab ility for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. the products described in this document are designed, developed and manufactured as contemplated for general use, including wit hout limitation, ordinary industrial use, general office use, persona l use, and household use, but are not designed, developed and m anufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a ser ious effect to the public, and could lead directly to death, personal injury , severe physical damage or ot her loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile la unch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersi ble repeater and artificial satellite). please note that fujitsu semiconductor will not be liable against you and/or any thir d party for any claims or damages aris- ing in connection with above-men tioned uses of the products. any semiconductor devices have an inherent ch ance of failure. you must protect against in jury, damage or loss from such failure s by incorporating safety design measures into your facility a nd equipment such as redundancy, fi re protection, and prevention of over- current levels and other abnormal operating conditions. exportation/release of any products described in this document may require necessary procedures in accordance with the regulati ons of the foreign exchange and foreign trade control law of japan and/or us export control laws. the company names and brand names herein are the trademarks or registered trademarks of their respective owners. edited: sales promotion department

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